Pipelining and hazards

In 1981 John Hennessy and his graduate students at Stanford began a processor project called MIPS, for Microprocessor without Interlocked Pipeline Stages. Its design centred on a five-stage pipeline, and the name stated a bold choice: instead of hardware that detected conflicts between instructions and stalled, the compiler was responsible for ordering instructions so that conflicts never happened.

Later processors brought the interlocks back in hardware, but the five stages of that design became the model taught in nearly every architecture course.